Next-Gen 3D Chip/Packaging Race Begins

The first wave of chips is hitting the market using a technology called hybrid bonding, setting the stage for a new and competitive era of 3D-based chip products and advanced packages.

AMD is the first vendor to unveil chips using copper hybrid bonding, an advanced die-stacking technology that enables next-generation 3D-like devices and packages. Hybrid bonding stacks and connects chips using tiny copper-to-copper interconnects, providing higher density and bandwidth than existing chip-stacking interconnect schemes.

AMD is using hybrid bonding technology from TSMC, which recently updated its roadmap in the arena. Intel, Samsung and others are also developing hybrid bonding. And besides AMD, other chip customers are looking at the technology.

“TSMC says its technology will likely be adopted by all of their high-performance computing customers,” said Charles Shi, an analyst at Needham. 

“Hybrid bonding is also on everybody’s roadmap, or at least on everybody’s radar, in mobile applications.”

A relatively new process conducted in a semiconductor fab, copper hybrid bonding is an advanced chip stacking technology that promises to give chip customers some competitive advantages. To be sure, chip stacking isn’t new and has been used in designs for years. What’s new is that hybrid bonding enables near monolithic 3D designs.

Most chips don’t require hybrid bonding. For packaging, hybrid bonding is mainly relegated for high-end designs, because it’s an expensive technology that involves several manufacturing challenges. But it gives those chipmakers some new options, paving the way towards next-generation 3D designs, memory cubes or 3D DRAMs, and more advanced packages.

There are several ways to develop these types of products, including the chiplet model. For chiplets, a chipmaker may have a menu of modular dies in a library. Customers then can mix-and-match the chiplets and integrate them in an existing package type or new architecture. In one example of this methodology, AMD stacked two internally-developed chiplets — a processor and SRAM die — resulting in a 3D package that combines a high-performance MPU with cache memory on top. The dies are connected using hybrid bonding.

There are other ways to implement chiplets. Traditionally, to advance a design, vendors would develop a system-on-a-chip (SoC) and integrate more functions on the device at each generation. This chip scaling approach is becoming more difficult and expensive at each turn. While it remains an option for new designs, chiplets are emerging as an alternative for developing complex chips.

With chiplets, a large SoC is broken up into smaller dies or IP blocks, and re-aggregated into a completely new design. In theory, the chiplet approach accelerates time-to-market with lower costs. Hybrid bonding is one of many elements to enable the technology.